The present invention relates generally to electronic components such as semiconductor wafers and more particularly, to a hierarchical architecture in a 3D integration scheme for multiple integrated circuit (IC) chips in which a global circuit and a local circuit on a front side of the IC chip is coupled to a global signal line on a back side of the IC chip with an arrangement of inter-wafer and intra-wafer through silicon vias (TSVs).
As packaging density in semiconductor devices continues to increase in order to accommodate more devices into a package, three-dimensional (3D) chip stacking technology has become more widely used in the industry. Typically, a semiconductor wafer includes several layers of integrated circuitry (IC) (e.g., processors, programmable devices, memory devices, etc.) built on a silicon substrate. A top layer of the chip may be connected to a bottom layer of the wafer by through-silicon vias (TSVs) or interconnects. In order to form a 3D chip stack, two or more wafers are placed on top of one another and bonded.
3D chip stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (SOC) solutions. In addition, the 3D chip stacking technology may provide other functionality to the chip. SOC architectures formed by 3D chip stacking can enable high bandwidth connectivity of products such as, for example, logic circuitry and dynamic random access memory (DRAM), that otherwise have incompatible process flows. At present, there are many applications for 3D chip stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.